1. Field of the Invention
The present invention relates an analog memory preferably for use in a Y/C separation circuit.
2. Description of the Related Art
The following description sets forth the inventor's knowledge of related art and problems therein and should not be construed as an admission of knowledge in the prior art.
An analog TV signal is represented by a NTSC (National Telecision Standards Committee) type signal, a PAL (Phase Alternation by Line) type signal, and a SECAM (SEquential Color and Memory). Such analog TV signal is transmitted as a composite signal SC in which a luminance signal Y showing brightness of a screen and a chrominance signal showing light and shade of a screen color are composed.
In analog TV signal processing, a Y/C separation circuit plays an important role for separating a transmitted composite signal SC into a luminance signal Y and a chrominance signal C.
The luminance signal Y is represented by the signal strength of the DC component of the composite signal SC. On the other hand, the chrominance signal C is superimposed on the luminance signal Y with the phase shifted by 180 degree every one horizontal line (see FIG. 3).
Thus, as shown in FIG. 4, by adding one of horizontal line to the other horizontal line with the one of horizontal line delayed by one horizontal scanning time, a trap filter for extracting only the luminance signal from the composite signal SC can be constituted. On the other hand, by subtracting one horizontal line from the other horizontal line with the one horizontal line delayed by one horizontal scanning time, a bandpass filter for extracting only the chrominance signal C from the composite signal SC can be constituted. Thus, a Y/C separation circuit requires an analog memory for delaying the composite signal SC.
An example of a conventional analog memory is shown in FIG. 5. In FIG. 5, only four sets of switched capacitor portions are illustrated for the sake of simplified explanation. In actuality, however, the switched capacitor portions SC are provided by the number corresponding to the delay time required for the input signal Vin.
In each switched capacitor portion SC1-SC4, the capacitive element C1-C4 is configured to charge and discharges the electric charges corresponding to the input signal Vin. On end of the switched capacitor portion SC1-SC4 is commonly connected to the source of the first MOS transistor Min1-Min4 and that of the second MOS transistor Mout1-Mout4 and the other end is grounded. The drain of each first MOS transistor Min1-Min4 is connected to the charge line Lin to which an input signal Vin as an delay object is applied. On the other hand, the drain of each second MOS transistor Mout1-Mout4 is connected to the non-inverting input terminal of the operational amplifier OP via the discharge line Lout. In the operational amplifier OP, the inverting input terminal (+) and the output terminal are connected in a negative feedback arrangement.
In each switched capacitor portion SC1-SC4, the first MOS transistor Min1-Min4 functions as a charge switch for charging the capacitive element C1-C4 in accordance with the input signal Vin. On the other hand, the second MOS transistor Mout1-Mout4 functions as a discharge switch for discharging the capacitive element C1-C4.
In this structure, the gates of the first and second MOS transistors Min1-Min4 and Mout1-Mout4 are on-off controlled, so that the input voltage Vin is outputted to the operational amplifier OP with the input voltage delayed by the switching cycle.
Japanese Unexamined Laid-open Patent Publication No. 2006-186562 can be exemplified as the related reference.
In the aforementioned analog memory, the discharge line Lout is connected to each of the drains of the second MOS transistors Mout1-Mout4 constituting the switched capacitor portions SC1-SC4. Thus, each of the second MOS transistor Mout1-Mout4 has a potential parasitic capacitance of a few femto (F) between the drain and the substrate.
It seems that the parasitic capacitance can be neglected because of the pico order capacitance value of each capacitive element. As mentioned above, however, the switched capacitor portions SC are provided by the number corresponding to the delay time required for the input signal Vin. For example, in cases where the input signal Vin is a composite signal SC containing a superimposed chrominance signal having a center wave of 3.58 MHz, in order to perform the sampling of the composite signal SC at the sampling frequency four times of the chrominance signal frequency, in the NTSC type, a total of 911 pieces of switched capacitor portions SC are provided to perform the sampling for one horizontal line since the horizontal scanning frequency is 15.734 Hz. In this case, the discharge line Lout is connected to the drains of 911 second MOS transistors Mout, resulting in a total large parasitic capacitance potentially existed in the discharge line Lout. This large parastic capacitance causes unignorable large errors between the input signal Vin and the output signal Vout.
The description herein of advantages and disadvantages of various features, embodiments, methods, and apparatus disclosed in other publications is in no way intended to limit the present invention. For example, certain features of the preferred embodiments of the invention may be capable of overcoming certain disadvantages and/or providing certain advantages, such as, e.g., disadvantages and/or advantages discussed herein, while retaining some or all of the features, embodiments, methods, and apparatus disclosed therein.